1. Field of the Invention
The present invention relates to a circuit board and a method for manufacturing the same, and, especially, to a circuit board having fine circuits and a method for manufacturing the same.
2. Description of Related Art
Customer demands of the electronics industry continue to evolve rapidly and the main trends are high integration and miniaturization. In order to satisfy those requirements, especially in the packaging of semiconductor devices, development of circuit boards with the maximum of active and passive components and conductive circuit layers has progressed from double-layer to multi-layer types. This means that a greater circuit layout area is available due to interlayer connection technology so that the requirement of high-density integrated circuits can be satisfied. Therefore, the thickness of package substrates will be lessened, and more circuits and electric components can be included in the package substrates in the same area unit.
For the purpose of satisfying operation requirements from efficient chips of microprocessors, chip sets, graphics chips, and application-specific integrated circuits (ASIC), semiconductor package substrates have to improve communication of chip signals, bandwidth, and impedance so as to promote the development for high density I/O counts packages. Otherwise, package substrates are required to move towards fine circuits and small vias so as to benefit developments of compact dimension, multifunction, high speed, high circuit density, and high frequency. Nowadays, in conventional processes of semiconductor package substrates, circuit dimensions have been decreased from 100 μm to 30 μm or less. Besides, line width, line space, and aspect ratio have also been decreased under better alignment accuracy.
Built-up structure technologies have developed to advance circuit density of semiconductor package substrates. In other words, through built-up structure technologies, dielectric layers and circuit layers are stacked together on a surface of a core circuit board. In addition, conductive vias are disposed in the dielectric layers so as to interconnect the different circuit layers. Nevertheless, built-up structure technologies are the key point influencing circuit density of semiconductor package substrates. Currently, semi-additive processes (SAP) are generally used to fabricate built-up structures.
With reference to FIGS. 1a to 1f, there is a flow chart of semi-additive processes. First, a core board 10 is provided in FIG. 1a. A circuit layer 11 is formed on the upper and lower surfaces of the core board 10. A plurality of plated through holes 101 are formed in the core board 10 so as to conduct to the circuit layer 11 on the upper and lower surfaces of the core board 10, and those plated through holes 101 are filled with resin 12. As shown in FIG. 1b, a dielectric layer 13 is formed to totally cover the surfaces of the circuit layer 11 and the core board 10. Subsequently, a plurality of vias 131 are formed on the dielectric layer 13 in order to expose parts of the circuit layer 11 to serve as conductive pads 111 with reference to FIG. 1c. A seed layer 16 is formed on the dielectric layer 13 and inside the vias 131. Then, a patterned resistive layer 14 within open areas 141 is formed on the seed layer 16 in FIG. 1d. The whole core board 10 is put into an electroplating tank (not shown in figures). A metal layer is electroplated in the open areas 141 of the patterned resistive layer 14 by using the seed layer 16 as a conductive path of an electric current. As shown in FIG. 1f, the patterned resistive layer 14 is removed. Additionally, parts of the seed layer 16, covered by the patterned resistive layer 14, are removed by etching so that another circuit layer 151 and a plurality of conductive vias 152 are obtained. Herein, by way of repeating the foregoing processes to manufacture dielectric layers and circuit layers, a circuit board with multilayer built-up structure can be fabricated. However, some open areas 141 of the resistive layer 14 located above the vias 131 have to be greater than the vias 131 because of alignment accuracy in photolithography. Therefore, the conductive vias 152 manufactured through an electroplating process are surrounded by annular metal rings 152a which connect to the circuit layer 151 as shown in FIG. 1g (a top view of the dotted circle A in FIG. 1f).
In the foresaid SAP, the line width of the etched circuit layer 151 becomes less than that of the predetermined circuit layer 151 because the seed layer 16 covered by the patterned resistive layer 14 has to be removed by etching. Accordingly, the required stable quality of the circuit layer can not be achieved. In addition, inappropriate narrow circuits are manufactured under unstable manufacturing processes resulting in circuits being damaged. However, if the predetermined width of the circuit layer 151 is increased for avoiding the condition mentioned above, that will depart from the purpose for manufacturing fine circuits. Moreover, line space is also occupied by the annular metal rings 152a surrounding the conductive vias 152 so that the built-up structure with the circuit layer 151 on the surface of the dielectric layer 13 nowadays still has its bottlenecks unable to promote the processes capability of the fine circuits.